The present invention relates to flash memory devices, and more particularly to a page buffer circuit and a program operation method.
In general, the read and program operations of a flash memory device are executed one page at time using a page buffer circuit. The construction and operation of the page buffer circuit in the related art will be described below.
FIG. 1 is a schematic circuit diagram of a page buffer circuit of a flash memory device in the related art. A page buffer circuit 10 includes a bit line selection circuit 11, a precharge circuit 12, a first register 13, a second register 14, a data input circuit 15, a data transmission circuit 16, a data output circuit 17, a first verification circuit 18, and a second verification circuit 19. The first register 13 includes a first sensing circuit 31, a first latch circuit 32, and a first reset circuit 33. The second register 14 includes a second sensing circuit 41, a second latch circuit 42, and a second reset circuit 43.
The program operation process of the flash memory device including the page buffer circuit 10 will be described in short below. The data input circuit 15 receives input data Din from an I/O node YG1 and outputs the data to the first latch circuit 32. The first latch circuit 32 stores the input data Din and outputs the stored data as program data. The precharge circuit 12 precharges a sensing node S to a set voltage in response to a precharge control signal PRECHb. Thereafter, the data transmission circuit 16 outputs the program data to the sensing node S. The bit line selection circuit 11 outputs the program data, which is received from the sensing node S, to a memory cell (not shown) connected to a selected bit line (for example, BLe1). As a result, when a program voltage is applied to the gate of the memory cell, the program data is programmed into the memory cell.
After the memory cell has been programmed, a program verification process is used to determine whether the memory cell has been correctly programmed. In the program verification process, when the read data from the memory cell is transmitted to the sensing node S, the first register 13 senses the read data and stores the sensing data. The first verification circuit 18 generates a verification signal VF1 in response to the sensing data. Thereafter, an external control circuit (not shown) shown in FIG. 1 determines whether the memory cell has been correctly programmed according to the logic value of the verification signal VF1. If the memory cell has not been correctly programmed, the memory cell is reprogrammed. When the memory cell is reprogrammed, sensing data having the same logic value as the input data Din is stored in the first register 13 in a previous program verification process. Accordingly, the first register 13 outputs the sensing data as the program data. As a result, the memory cell is programmed.
Meanwhile, if the memory cell has been correctly programmed in the program verification process, the logic value of the sensing data stored in the first register 13 is different from that of the input data Din. In other words, when the first register 13 senses the read data from the memory cell in the program verification process, the logic value of data (i.e., input data Din) stored in the first register 13 in a previous program process is inversed. Accordingly, when a program operation is performed on the remaining memory cells (hereinafter, referred to as “second memory cell(s)”) except for the memory cell (hereinafter, referred to as “first memory cell”), the first register 13 outputs the data inversed in the previous program verification process (i.e., sensing data having a logic value ‘1’different from a logic value ‘0’ of the input data Din) as program-inhibit data. As a result, the programming of the first memory cell is inhibited.
Thereafter, when the program verification process is executed again, the logic value ‘1’ of the inverted data stored in the first register 13 keeps intact without regard to a data value read from the first memory cell. Accordingly, although the program verification process is normally executed repeatedly, the same result is obtained if the program verification operation had not been performed on the first memory cell. As described above, in the program operation process on the page buffer circuit 10, the program verification operation and the program operation are no longer performed on a memory cell once it has been determined to be correctly programmed.
However, during the read operation for the program verification, there may be a case where the data (i.e., the input data Din) stored in the first register 13 is inverted even though a memory cell has not been actually programmed. This may be caused by noise, etc. within the page buffer circuit 10. Another possibility is when the threshold voltage of the programmed memory cell is substantially the same as the verification voltage (i.e., when the memory cell is not sufficiently charged).
In this case, the program verification operation and the program operation are no longer performed on a memory cell in which the program operation has not been completed. Accordingly, failure occurs in the program operation.